Nvidia Senior STA Engineer 

Israel, Tel Aviv District, Tel Aviv-Yafo 

640704709

What you'll be doing:

• Own the full chip STA, analyze the timing results, verify correctness and provide budget for the different partitions.
• Generate the timing constraints of complex interfaces for the STA and the P&R flow.
• Be exposed and work on a variety of exciting designs (including high cell count and high frequency), resolving complex timing and congestion problems.
• Help to shape the SoC clock tree, and effect the work of the different teams (Front end, DFT & BE).
• Daily work involves all aspect of STA & chip design: take part in SDC generation & review, actively running & analyzing STA tools, guiding the group during chip closure process, etc'.
• Taking part inflows development.
• Take part in ramping up new breaking technologies.

What we need to see:

• B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.
• 5+ years proven experience in RTL2GDS flows and methodologies.
• Knowledge in physical design flows and methodologies with emphasis on STA (PNR, STA, physical verification).
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
• Excellent teammate.