Microsoft Senior Logic Design Engineering Manager 

India 

633696645

Qualifications:

• BS/MS in Electrical Engineering or Computer Science/Engineering
• 8+ years logic design experience as a part of either CPU, Cache, Fabric, Digital Power Management, DVFS, Sensors, PCMs, Debug, Peripherals and/or SoC development
• 5+ years of Management Experience
• Knowledge of logic design flow including RTL coding, Synthesis, timing constraints, timing closure.
• Demonstrated expertise in Computer Architecture, Digital Design, IP/SoC design principles as part of SoC and/or IP development.

Additional Preferred Qualification:

• Highly Proficient in Verilog/System Verilog coding constructs.
• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
• Demonstrated experience and knowledge of clock crossings, and power/UPF in design
• Ability to write scripts using Perl, Tcl, Python etc.
• Familiarity with Industry standard interface protocols is a plus.
• Familiarity with Formal Equivalence Verification and Power Analysis is a plus.
• Excellent verbal and written communication skills.

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

In this role, you will be managing team of logic design engineers and will require manager to be hands-on; being an integral part of Logic Design Team’s micro-architecture implementation, RTL Coding, IP & subsystem development, and integration to SOC along with design quality assurance for our projects. Your roles and responsibilities include:

• Managing and leading team of Logic Design Engineers delivering cutting edge IP and Subsystem Design
• Implement the micro-architectural specification in Verilog or System Verilog
• Continue to grow your micro-architectural knowledge and contribute to unit, sub-system and SOC micro-architecture.
• Development and Integration of various functional block RTL into SoC RTL
• Perform design quality checks such as Timing closure, Synthesis, Lint, CDC, Low Power Intent.
• Interface with verification team to ensure functional correctness. Interface with performance modeling, physical design, design-for-test, and other teams to deliver qualified physical partitions evaluating tradeoffs and delivering high quality design.
• Exercise the functionality of the block by writing basic tests and debug for various features at IP and SoC levels as deemed necessary. Automate tasks using scripting for efficiency
• Delight your customers by providing high quality functional blocks on schedule and with professional integrity
• Challenge the status quo with growth mindset.
• Mentor team members and summer interns for a growing team