Intel Experienced Verification Design Engineer 

Israel, Haifa District 

617072782

Qualifications:

A B.Sc. or M.Sc. degree in Electrical Engineering, Computer Engineering, Software Engineering or Computer Science.
At least 5 years of overall experience performing RTL Verification and/or logic design using System Verilog.
Knowledge in Very Large-Scale Integration (VLSI) design and/or verification
Experience in developing validation collaterals in emulation environment - Advantage.
Experience in developing Register Transfer Level (RTL) validation environment -- Advantage.
Experience in working with Verilog/SVTB/OVM/UVM and Specman -- Advantage.
Experience with Formal Verification CPU usage.
Familiarity with CPU X86 architecture.

Experienced HireShift 1 (Israel)Israel, Haifa