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Google Microarchitecture RTL Lead Silicon AI/ML TPU Google Cloud 
India, Karnataka, Bengaluru 
6119123

18.09.2024
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel.
  • 4 years of experience in people management, developing employees.
  • Experience in micro-architecture and design of Machine Learning IPs or Graphics IPs, handling Low Precision/Mixed Precision Numerics.
  • Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:
  • Experience with programming languages (e.g., Python, C/C++ or Perl).
  • Experience in SoC designs and integration flows.
  • Knowledge of neural networks, arithmetic units, processor design, accelerators, bus architectures or memory hierarchies.
  • Knowledge of high performance and low power design techniques.