Marvell Software System Test Engineer Intern 

Germany, Baden-Württemberg 

609370162

What You Can Expect

• Ownership of complex design blocks and complete analog macros.
• Design and develop high-speed and low-power analog mixed-signal circuits in advanced CMOS technologies, with a focus on SerDes(Serializer/Deserializer)die-to-die communication, and high-speed wireline design in general.
• Lead and contribute to the design of ADCs, DACs, Regulators, Clock Generation and Distribution, DLLs, Custom high-speed digital circuits, CTLE, VGA, and TX Drivers.
• Cooperate with system and architecture team in identifying the optimal circuit solution based on overall cost function
• Supervise, coach and provide technical direction to more junior engineers
• Supervise and guide layout activities to ensure design accuracy and performance.
• Conduct post-silicon testing and validation of analog mixed-signal circuits.
• Collaborate with cross-functional teams to ensure successful project execution.
• Prepare and maintain detailed documentation of design processes and results.
• Participate and lead design reviews to ensure design quality and compliance with project requirements.
  

What We're Looking For

• MS/PhD in Electrical Engineering and 10+ years of demonstrated experience in high-speed and low-power design on advanced CMOS technologies, specifically in one or more of the following areas: ADC, DAC, voltage regulators, clock generation and distribution circuits, DLLs, custom high-speed digital circuits, CTLE, VGA, and TX drivers.
• Proven track record of successfully bringing multiple tape-outs to production.
• Ability to independently assess design trade-offs and select the best one based on business needs and implementation risk.
• Ability to identify, analyze, and resolve complex design challenges and issues, ensuring robust and reliable circuit performance.
• Ability to technically coordinate the work of junior employees, providing mentorship and guidance.
• Experience in overseeing layout engineers, providing guidance on best practices, and ensuring that layout designs meet performance, area, and reliability requirements.
• Proficiency in post-silicon validation, including hands-on experience with lab equipment, debugging, and characterization of analog mixed-signal circuits.
• In-depth knowledge of CMOS process technology, device physics, and the impact of process variations on circuit performance.
• Proficient in using electronic design automation (EDA) tools for schematic capture, simulation, layout, and verification, such as Cadence, Synopsys, or Mentor Graphics.
• Very good understanding of related areas such as RTL, Firmware, Design Verification, Design for Test, and Physical Design.
• Strong communication and teamwork skills.

Expected Base Pay Range (USD)

165,630 - 248,100, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at