Intel CPU Physical Design-Timing Lead Engineer 

India, Karnataka, Bengaluru 

609265930

Your responsibilities will include but not limited to:

1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs.

2. Deep understanding of Static timing analysis concepts

3. Timing Convergence across all HVM targets

4. Closely work with SD, Integration and Floor plan teams

Qualifications

• You must possess a master’s degree in electrical or Electronics Engineering with at least 8 or more years of experience in related field or a bachelor’s degree with at least 10 years of experience.
• Technical Expertise in Static Timing Analysis is preferred.

• Should have minimum of 2 years experience in leading the Team of at least 3-4 people

Preferred additional skills

· Experience of handle complex core design, high-speed designs

· Timing signoff flows/tools experience both/either Synopsys/Cadence tools

· Very good knowledge on Timing tools, flows and methodology

· Ability to handle new feature feasibility studies

· SD flow knowledge would be plus

· Familiarity with Verilog/VHDL

· Tcl, Perl, Python scripting

· Strong verbal and written communication skills