Advanced knowledge of standard ASIC verification flows including simulation and testbench development.
Knowledge about industry standards and practices in PHY Design, including RTL writing, verification tools of RTL.
Deep Understanding of all aspects of PHY construction, Integration and Physical Design.
Working knowledge of Extraction and STA methodology and tools.
Excellent knowledge of System Verilog, Verilog.
Good knowledge of C / C++.
Experience with either Perl/Tcl scripts.
Knowledge of industry standard interfaces and experience with multiple frontend simulators/debuggers.
Deep understanding of Design methodology to debug issues at PHY level.
A teammate with excellent interpersonal skills and the desire to pursue diverse challenges.
Education & Experience
BS.c / MS.c EE or BS.c / MS.c CE
Additional Requirements
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