Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.
5 years of experience in CMOS technology development.
Experience in CMOS device characterization, process integration and modeling/simulation.
Statistical analysis experience in JMP
Preferred qualifications:
PhD degree in Electrical Engineering with a specialization in semiconductors/microelectronics or equivalent practical experience.
7 years of experience in the Foundry and Fabless environment.
Experience in product-level testing in SoC including yield and parametric evaluation.
Excellent work ethic, communication and time management skills.