Qualcomm Design Implementation engineer - Sr Lead/Staff 

India, Telangana, Hyderabad 

585016783

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

Responsiblities:

• Full chip synthesis using Synopsys Design Compiler and Design Compiler-Topographical

• Constraints development, Static Timing Analysis & timing closure

• Work closely with design team to come up with preplacement requirements & timing constraints

• Work closely with physical design team for floorplan, placement & timing reviews

• Work closely with cross-functional teams to review standard cell profile, timing models & memory models

Skills/Experience:

• 4 to 8 years of experience in digital design

• Good understanding of SoC ASIC design flow

• Hands on experience in full chip synthesis and static timing analysis

• Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a must

• Good knowledge of IO interfaces like DDR, SDCC, HSIC, SPI is a must

• Knowledge of ARM Processors, Ethernet MAC, PCIE and Bus protocols like AHB, AXI etc desirable

• Experience in Perl, TCL and shell scripting is desirable

• Excellent interpersonal & analytical skills with ability to work independently

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.