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Microsoft Senior Silicon Engineer 
Taiwan, Taoyuan City 
581812831

08.05.2025

As a Senior Silicon Engineer in the Data Processing Unit team you will be validating silicon to solve complex problems in a datacenter. You will interact with the architecture team to develop a programmable silicon implementation. This position is expected to be highly visible and impactful. The vast breadth of domains required to build our DPU silicon gives the perfect opportunity to experience different areas of expertise. The depth required to solve complex engineering problems utilizes your experience and provides you with the perfect platform to shine and grow to the next stage in your career.

Required Qualifications:

  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
    • ORMaster's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
    • OR Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
    • ORequivalentexperience.
  • 5+ years of experience with RTL design and/or architecture experience.
  • 5+ years of experience of DDR4~5 or LPDDR5 Protocols, Cache design or Inter-Cluster Cache Coherency, like MESI protocol.

Other Requirements:

  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:
  • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

  • Hands-on experience in integrating 3rd party IP, such as DDR Controller/PHY and PLLs.
  • Proven experience and understanding of Clock Domain Crossing design techniques.
  • Proficiency in Verilog, System Verilog, Synthesis and Static Timing Analysis.
  • Self-motivated and able to work effectively both as an individual and as part of a team.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until May 13, 2025.


Responsibilities
  • Own the micro-architecture specification and RTL development of design modules for ASIC memory subsystem.
  • Review and provide feedback on verification plans and methodology.
  • Collaborate with Physical design teams to ensure design meets timing and area requirements.
  • Work on post-silicon verification and debug.