What you’ll be doing:
You will be in charge of state of the art Design for Test (SCAN INSERTION) flows and implementation
Take full SCAN INSERTION ownership end to end on a project, from Arch & planning to implementation and verification
Inventing and maintaining automation flows that provide SCAN INSERTION implementation to project
What we need to see:
4+ years of hands on DFT/ATPG/SCAN experience knowledge & technical experience in DFT ASIC Design and in ATPG/SCAN tools(DC/Fusion/Genus)
Strong programming skills in scripting languages
BSc. in Electrical Engineering or Computer engineering
Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility
Ways to stand out from the crowd:
Knowledge of DFT including SCAN INSERTION, BIST, on-chip scan compression, fault models, ATPG, and fault simulation
Experience in Synopsis/Mentor SCAN tools
Programming languages: TCL, PRL, Phyton & Unix shell scripts
משרות נוספות שיכולות לעניין אותך