Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
3 years of experience in Design Verification, verifying digital reasoning at Register-Transfer Level (RTL) level using C/C++, SystemVerilog or Universal Verification Methodology (UVM).
Experience in verifying digital systems using standard Internet Protocol (IP) components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Experience in creating and using verification components and environments in standard verification methodology.
Experience in coding languages and software development frameworks.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering or Computer Science, or equivalent practical experience.
5 years of experience with architecture in Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock and Power Controllers.
Experience with Interconnect protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL) with performance verification of System on a Chip (SOCs), pre-silicon analysis and post-Silicon correlation.
Experience with building verification methodologies with simulation, emulation and Field Programmable Gate Array (FPGA) prototypes.