Western Digital Technologist ASIC Development Engineering RTL Design 

Philippines, Quezon City 

567639198

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

SOC Design Engineer - Job Description

You should have strong knowledge and experience with all aspects of the SOC design and implementation flow – including datapath design, low power design, clock and reset schemes, coverage driven verification, synthesis, P&R, STA, DFT, power-islands, floor-planning, CTS, IR-drop – and an understanding of how architecture decisions impact these flows. You will be responsible for developing, contributing, and leading ASIC macro and micro-architecture activities in our storage-based controllers. You should be highly motivated with strong communication skills, attention to detail, and quality oriented. Candidates with a take-ownership attitude will succeed in this role.

it is a hands-on SOC design implementation role.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Strong knowledge in IP/SOC design methodologies.
• Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog
• Strong experience in Synthesis, timing, full chip netlist & front-end design tools& flows Low power design
• Mentoring juniors and enhancing their skill set
• Expert knowledge on code coverage, functional coverage, Lint, CDC etc
• Power Analysis based on RTL/Netlist including early power estimation based on previous generation architectures
• Defining requirements for ASIC design, verification, and physical implementation teams
• Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions
• Reviewing and configuring 3rd party IPs
• Supporting other teams in the ASIC organization and reviewing their work
• Supporting product teams with documentation, code-reviews, and silicon debug
• Continuously finding opportunities for improving design quality and design practices

Qualifications

• Bachelor/ Master degree in Electronics/VLSI/Micro-Electronics Engineering
• 10+ years of ASIC Design/Architecture experience with strong knowledge of USB, SD, PCIe + NVMe and/or UFS in a storage application
• RTL design experience in Verilog/SystemVerilog
• Knowledge and experience in various aspects of SOC design, verification, and implementation flows
• Experience with low-power design techniques
• Ability to read and understand SW code
• Understanding of CPU and memory architectures, datapath pipelining mechanisms, distributed system design, ASIC low-power implementations, clock and reset methodologies
• Excellent Logic design and debug skills; proficiency in protocols like SATA/USB/PCIe; knowledgeable in bus protocols like AHB/AXI/I2C/UART/JTAG/CJTAG
• Should work with Verification, FW, Validation, Analog, IO, Physical Design, ATE test, Chaz and Quality teams to architect, design and debug