המקום בו המומחים והחברות הטובות ביותר נפגשים
Key Responsibilities:
Develop and maintain advanced test benches and verification environments using System Verilog and UVM.
Engage in the end-to-end verification process of complex ASIC design blocks.
Create comprehensive test plans and coverage points to ensure robust verification.
Upgrade and refine test benches to integrate new features seamlessly.
Lead and contribute to emulation testing efforts, ensuring the highest quality in our products.
What You'll Bring:
A Bachelor’s or Master’s degree in Electrical & Electronics Engineering (EE) or Computer Engineering (CE).
1 to 3 years of relevant professional experience with System Verilog based verification (outside of internship)
Benefit from a competitive salary, comprehensive benefits, and a flexible work culture.
משרות נוספות שיכולות לעניין אותך