Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with programming languages such as Perl, Python, or TCL.
Experience in managing block physical implementation and Quality of Results (QoR).
Experience with Application-Specific Integrated Circuit (ASIC) Register-Transfer Level to Graphic Data System (RTL to GDS) implementation for high PPA designs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science with computer architecture.
Experience with constraints, synthesis or Clock Tree Synthesis (CTS).
Experience with 7/5/3/2nm node.
Knowledge of Register-Transfer Level to Graphic Data System II (RTL to GDSII) in innovus or cadence tools.
Knowledge of Electromigration IR Drop (EMIR), Static Timing Analysis (STA), Photon Doppler Velocimetry (PDV), Logic Equivalence Check (LEC) and VC Low Power (VCLP) flows.