What you will be doing:
Work in a combined design and verification team which develops core units within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.
What we need to see:
B.SC./ M.SC. in Computer Engineering /ElectricalEngineering/CommunicationEngineering or equivalent experience
3+ years of proven experience in RTL FrontEnd Asic Verification (Chip Design)
Deep and vast experience with System-Verilog UVM.
Ability to technically lead the verification of an IP block
Familiarity with the different verification tools and methodologies.
Deep knowledge in HDL (Verilog/VHDL)
High Level English
משרות נוספות שיכולות לעניין אותך