Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with physical design flow such as constraints, synthesis, floor planning, place and route, clock tree synthesis (CTS), or physical verification.
Experience with low-power design techniques, such as power gating, clock gating, or voltage scaling.
Experience with hardware description languages (RTL) such as verilog and systemverilog.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
Experience with scripting languages such as Perl, Python, or Tcl.
Knowledge of Circuit design, device physics, and submicron technology.