Nvidia Senior ASIC Design Engineer Clocks 

Taiwan, Taiwan Province, Hsinchu 

517665022

What you’ll be doing:

• As a Clocks team member, you will need to run and enhance some in-house flows to guarantee the good quality of clocks RTL and netlist, drive the issues to close.

• You need collaborate with frontend team to make sure the clock structure follows some predefined rules.

• And work with backend team to make sure the clock is distributed/routed correctly. We have some special check for transition/skew, etc.

• You will use Perl/Python to improve the productivity.

What we need to see:

• BS or (MS preferred) in EE with 4+ years of meaningful work experience.

• Ability to thrive in a dynamically changing environment.

• Strong coding skills in Perl or Python or other industry-standard scripting languages.

• Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.

• Good understanding of backend flows and requirements is a plus.

• DFT knowledge is a plus.

• Experience in implementing on-chip clocking networks is desirable.

Ways to stand out from the crowd:

• Excellent analytical and problem-solving skills.

• Fluent English (both written and spoken) and excellent communication skills.

• Good team work spirit, easy to cooperate with team members.