What you'll be doing:
Work with various Arch & Design teams to come up with test plans for system level power & performance optimization features and management controllers
Collaborate with other validation & bring up teams to bring up/characterize silicon and system level features.
Work with design & estimation teams to correlate with pre-silicon expectations.
Work with HW and SW teams to do the vital tuning and optimization of silicon power & performance controllers
Develop various system level control mechanisms together with Arch/Design/SW teams.
Debug silicon and system level issues and craft work around/fix as applicable to ship the product meeting time to market requirements.
What we need to See:
B. Tech or M. Tech in Electronics Engineering stream.
At least 5+ years of proven experience in silicon power architecture, system level design, validation, and power/performance optimization.
Strong understanding of aspects related to silicon power and performance, technology node impacts, Hardware and Software interactions at system level.
Hands-on experience with silicon bring up, validation and productization
Good knowledge in board and system design considerations, Power supply design.
Very good problem solving and hardware debugging skills.
Very good data analysis and logical reasoning skills.
Strong familiarity with HW lab environment and understanding of various lab equipment.
Experience in working with windows. Linux exposure is highly preferred.
Must be a great teammate and ready to collaborate with global teams from diverse cultural backgrounds in a high energy environment.
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