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Google Technical Lead ASIC IP Subsystem Design Silicon India, Karnataka, Bengaluru 510821269
31.07.2024
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience in ASIC design.
- Experience in RTL development with Verilog/SystemVerilog.
Preferred qualifications:
- Master's degree or PhD in Materials Science, Electrical Engineering, Computer Engineering, Physics, or a related field.
- Experience in high-performance design, multi power domains with complex clocking and multiple SoCs with silicon success.
- Proficient with micro architecture design.
- Knowledge of system design to develop highly optimized IPs with excellent PPA.
- Understanding of computer architecture including industry standard interfaces and memory subsystems.
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