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Western Digital Principal Engineer ASIC Development Engineering SOC Verification 
Canada, British Columbia, Area H (Cultus Lake/Columbia Valley) 
503884431

24.07.2024
Company Description

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

Job Description

As a Verification Engineer in SoC Development Team, you will develop test-plans and tests for use in testing complex System On Chip (SoC) ASIC’s. Your work will enable industry-leading data storage control SoC’s that get deployed into high volume consumer and enterprise products.

Essential Duties and Responsibilities:

  • Responsible for driving verification strategy, creating Test Plans, and developing Test Benches for SoC.
  • Collaborate with architects, designers, pre-and post-silicon verification teams to develop test plans
  • Responsible to develop C-based tests on SoC. Processor knowledge is a plus.
  • Define and meet all functional coverage goals
  • Run and debug gate-level simulations
  • Understanding and generation of functional patterns for ATE
Qualifications

:

  • BE or MS degree in Electrical Engineering or Computer Engineering, with 9 to 13 years of experience
  • Deep understanding of C, System Verilog UVM and coverage driven verification methodology
  • History of building and improving UVM based verification methodology

:

  • Develop and execute verification plans
  • Proficiency with C, Verilog & System Verilog and verification
  • Experience in implementing advanced test benches, verification models, scoreboards/checkers.
  • Knowledge in bus protocols - APB, AHB, AXI, and bus interconnects
  • Good Programming/Scripting skills with languages such as Python, Perl, TCL, and BASH
  • Experience with test plan creation and test-bench development
  • Experience with test development and test coverage assessment
  • Excellent debugging and problem-solving skill
  • Knowledge in various interfaces – PCIe, DP, UART, I2C, I2S, SPI, USB, SD
  • Create and modify SoC-level, and sub-system level test benches.
  • Experience in setting up and running gate-level simulations
  • Gate Level / Power-Aware simulations
  • Great written and verbal communication skills
  • Interest in ASICs, SoCs, hard disk drives, flash memory, semiconductor components
  • Strong team player who can collaborate with colleagues