Required Technical and Professional Expertise
- 18 plus years of relevant experience
- Experience with PCIe controller architecture/ microarchitecture/ RTL design – PCIe Gen 5/ Gen 6 and CXL2.0/3.0
- Good understanding of PCIe PHY
- Experience with integration of PCIe controller in high speed infrastructure
- Proficient in HDLs- VHDL must/ Verilog
- Experience in working with architecture/ FW/ SW teams
- Experience in High speed and Power efficient logic design
- Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage
- Good understanding of Physical Design and able to collaborate with physical design team for floorplanning, placement of blocks for achieving high-performance design
- Experience in leading uarch, RTL design teams for feature enhancements. Being a lead, ability – to quickly understand issues spanning multiple functional domains, switch context frequently, and provide solutions to problems, is necessary.
Preferred Technical and Professional Expertise
- Hardware development, Processor Backend Design