

What you’ll be doing:
Be involved in some design work for the IPs and features owned by System-ASIC team
Brainstorm with IP design owners to figure out suffering points or discuss infra-related improvement ideas. Settle down the specific requirement and choose the suitable methodology to develop infrastructure flow/tool
Responsible for Reset methodology work, include: utilize in-house or industry commercial tool and flow to guarantee reset design quality, develop new tool or flow to improve reset design quality and efficiency
What we need to see:
MS in EE/CE/CS
2+ years of design or design methodology experience
Strong coding skill for Python, Perl, TCL, JavaScript etc.
Understand ASIC design/verification flow and have experience forCDC/RDC/Synthesis/Timingclosure
Fluent English (both written and spoken) and excellent communication skills to interface with many groups and build consensus
Ways to stand out from the crowd:
Good team work spirit, easy to cooperate with team members
Has Web system, Database knowledge is a plus
Knowledge on deep-learning experience is a plus
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