Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related field, or equivalent practical experience.
5 years of experience in IC qualification, data review, production release, System Level Testing, test time reduction and yield improvement.
5 years of experience in IC testing, Yield and Bin Pareto Analysis.
Preferred qualifications:
7 years of experience in VLSI technologies, product and test engineering, and semiconductor processing.
Experience in system level testing using Advantest SLT platform.
Experience in ATE platforms such as Advantest 93K, Teradyne UltraFlex SOC test system.
Experience in SERDES, PCIe, DDR and Mixed-Signal circuits such as ADC, DAC, PLL, LDO and their performance measurements.
Experience in advanced packaging (i.e., 2.5d, InFo), and process technology (i.e., wafer sort, final test).
Experience in Design for Test (DFT) techniques and structural tests such as Scan/ATPG, JTAG and memory BIST, and familiarity with testing sensors such as PVT sensors, Temp sensors.