Nvidia Clock Design Engineer 

Israel, Tel Aviv District, Tel Aviv-Yafo 

473775351

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

• Designing and implementing SOC level clock requirements
• Developing and deploying automation flows which support SOC level design
• Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
• Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues

What we need to see:

• B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
• 3+ years of relevant experience in chip design
• Solid hands-on RTL design skills in Verilog
• Proficiency in at least one common scripting languages like python, bash, tcl.
• Great teammate.

:

• Passion for quality. Experience with delivery to physical design, emulation, firmware and other customers