Bachelor's degree in Electrical Engineering, Computer Science, a relevant technical field, or equivalent practical experience.
8 years of experience with DFT/DFD flows and methodologies.
Experience with DFT/DFM technique and well-versed in ATPG, MBIST, JTAG, Scan Compression, SSN and at-speed test.
Experience with silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG related issues.
Experience with post-silicon electrical/physical fault isolation.
Preferred qualifications:
Experience with scripting languages like Python, Perl, etc.
Experience with silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and diagnostics.
Knowledge of defect types, fault models, and low power design methodologies.
Ability to be motivated and collaborate with global teams.