Broadcom Layout Engineer 

Singapore, Singapore 

457554834

Job description:

Responsible to understand and apply all necessary layout guidelines (standard cells, I/O), new process rules and other technical requirements for quality layout.

Schedule time-line & layout floor-planning

Complete quality layout and verification within planned schedule (without supervision for experienced engineer)

Skill Set / Requirements:

Strong layout knowledge with a minimum of 3 to 4 years of experience is preferred. Fresh Bachelor Electronics engineering graduates or less than 3 years of layout experience may be considered.

Extensive experience in full custom and/or analog layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration (EMIR) in CMOS process.

Good experience in Floor-planning, hierarchy layout and chip integration.

Experienced in Cadence Layout tools VIRTUOSO (XL, VXL or EXL), and CALIBRE verification tools.

Good understanding of Latch-up and ESD in CMOS process and implementation for IO layout design.

Knowledge of Script Programming and SKILL Programming would be a plus.

Strong layout knowledge in submicron & Finfet process, e.g. 16nm, 7nm, 5nm, 3nm