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Apple FE Engineer United States, California, Cupertino 455821676
31.08.2024
Description
* Building a test bench, creating test vectors, and running the verification environment to verify that the subsystem you designed works properly* Synthesize the subsystem into logic and perform Static Timing Analysis (STA) on the design to make sure it meets the timing requirements* Designing, integrating, and verifying a system fabric bus into a subsystem
Minimum Qualifications
- * Digital Logic Design knowledge
- * Verilog/System Verilog RTL language design entry
- * Synopsys/Cadence synthesis
- * Synopsys PrimeTime Static Timing Analysis (STA)
- * Synopsys (VCS)/Cadence(Incisive) simulation
- * Strong problem solving and analytical skills
- * Strong communication skills combined with team-oriented approaches to own the verification efforts in a specific area of the design
Preferred Qualifications
- * Experience/exposure writing specifications and documentation
- * Experience/exposure with verifying logic design hardware
- * Experience/exposure to front-end tools and methodologies
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $58.61 and $88.29/hr, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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