Bachelor's degree in Electrical Engineering or equivalent practical experience.
10 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
Experience creating and using verification components and environments in standard verification methodology.
Preferred qualifications:
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Experience with verification techniques and the full verification lifecycle.
Experience with performance verification of ASICs and ASIC components.
Experience with ASIC standard interfaces and memory system architecture.