Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
8 years of experience in IC testing, Yield and Bin Pareto Analysis.
5 years of experience in IC qualification, data review, production release, System Level Testing, test time reduction, and yield improvement.
Preferred qualifications:
10 years of experience in the following areas: VLSI technologies, product and test engineering, and semiconductor processing.
Experience in System Level Testing using Advantest SLT platform.
Experience in Automatic Test Equipment (ATE) test platforms such as Advantest 93K, Teradyne UltraFlex SOC test system.
Experience in SERDES, PCIe, DDR and Mixed-Signal circuits such as ADC, DAC, PLL, LDO, and their performance measurements.
Familiarity with advanced packaging such as 2.5d, InFo, process technology, and how it relates to design and testing data analysis: wafer sort, final test.