Qualcomm ASIC/NoC CAD Design & Deployment Engineer - Qualcomm Guyancourt 

France, Ile-de-France 

442846164

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

Qualcomm France-QITC develop interconnect for complex SoCs providing low power, higher system bandwidth, grater IP flexibility, fewer global wires and easier timing convergence as well as faster time to market than existing bus interconnects. QITC NoC solution includes a full suite of automated NoC Design Tools that improve designer productivity.

Qualcomm Interconnect Technology (QITC) has been breaking ground in interconnect design for 15 years and continues to innovate and deliver technology in line with the very latest evolutions in SoC design.

Qualcomm France-QITC mission is to develop and deploy highly configurable custom-built interconnect hardware IPs, software tools, and exploration and verification methodologies so that SoC integration teams can quickly assemble SoCs with the desired Power Performance Area (PPA) characteristics.

To this end, QITC technology embraces the complete SoC infrastructure to provide increased SoC performance at minimal cost for integration. Our work is at the backbone of the SoC, interconnecting all major IP solutions.

You will participate to the deployment and definition of new CAD tools with highly skilled experts across different teams (Architecture, Hardware, ...) and external NoC Teams (San Diego, Bangalore,...)

Qualifications

• Knowledge of Industry EDA tools and PPA optimization techniques (Synthesis, Physical implementation flow, …)

• Good programming skills in Python, Tcl, C shell, BASH, make

• Experience with CAD automation and/or software development

• Experience with design timing convergence: either in P&R or STA using commercial/in-house EDA tools (DC, DCNXT, FC, Innovus, Primetime,…)

• Experience to automate manual operations with reusable tools

• Good communicator who can accurately describe issues and follow them through to completion

Minimum Qualifications

• Master’s degree in Microelectronics, Computer Science, or related field.

• Preferably 2-5 years of solid experience in SoC/ASIC design, architecture, new graduated will be considered upon strong internships & motivation.

• Hands-on experience with CAD Tool (Synthesis, Place & Route), script, Unix environment

What's on Offer

Apart from working in an open, relaxed and collaborative space, you will enjoy:

• Salary, stock and performance related bonus

• Maternity/Paternity Leave

• Employee stock purchase scheme

• Matching pension scheme

• Education Assistance

• Life, Medical, Income and Travel Insurance

• Subsidised memberships for physical and mental well-being

• Bicycle purchase scheme

• Employee run clubs, including, running, football, chess, badminton + many more

EDA, CAD flow, Synopsys Design Compiler, Cadence Innovus, Primetime, Synthesis, Place & Route, STA

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

PhD in Science, Engineering, or related field.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.