Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
20 years of experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.
Experience in leading chip development projects.
Experience in working with external ASIC vendors.
Preferred qualifications:
Master's degree or PhD in Engineering, or a related field.
Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
Knowledge of data centers and cloud markets, technological and business trends, requirements, and ecosystem partners.
Ability to motivate and focus a large collaboration to reach challenging goals.