A verification Engineer owns one or more architectural functional blocks on IP or SOC to perform all verification related tasks including creating test cases and test bench using UVM methodology.Responsibilities would include:o Develop pre-Silicon functional validation tests to verify system will meet design requirements.o RTL and GLS Simulation.o Create test plans for RTL validation, define and run system simulation models, and find and implement corrective measures for failing RTL tests.o Develop infrastructure with regressions and volume validation.o Identify, document test plans across various platforms - IP library, Complex-IPs and Subsystemso Participate and contribute to Verification infrastructure and methodology.o Adopting Verification tool flows and methodologies and translating the best-in-class verification methodologies from industry to internal deployment such as Formal Verification, Low Power Verification, Performance Verification, Co-Simulation.Qualifications:o Bachelor or Master's degree in Microelectronics, Electrical/Computer Engineering or Computer Scienceo Pre-Si Verification on Cores (x86, ARM, RISC cores)o Understanding industry standard interfaces and fabrics such as NOC, AXI, AHB/APBo Ability to work in a dynamic and team-oriented environmento Strong verbal and written communication skills.o Strong independence and proven ability to set and meet own goalsStudent / InternShift 1 (China)PRC, Shanghai
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.