Texas Instruments SOC Design Verification Engineer 

India 

413705316

Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. Additional job functions include analyzing equipment to establish operating data and conducting experimental tests and evaluating results to confirm the device meets all requirements in the specifications. You may also run software simulations, selecting components and equipment based on analysis of specifications and reliability. As a Design Verification Engineer you may also review vendor capability to support product development. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry.

About ASM Auto:

Responsibilities:

Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:

· Active involvement with architecture team during the spec definition phase

· SubSystem/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes.

· DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs

· Active collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities

· Final SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines

Qualifications:

• 2-5
years of DV experiencein SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations

Experience in one or many of the following: C based SOC DV, scripting (Python/Perl/Shell) knowledge, DV flow ownership for functional/Formal verification, UVM/System Verilog deep understanding, AMS/GLS/PAGLS/CPF/UPF based verification, Post silicon verification etc.

Strong in digital design fundamentals, computer organization & architectures and bus protocols

Excellent debugging skills with Verilog/VHDL designs

Thorough knowledge in one or many of the standard protocols. Ex: AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, PSI5, Flexray etc

Work experience on C based environment with ARM/DSP multi-processor-based systems including the power aware simulations is a big plus

Good problem-solving skills

Experience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows

Exposure to CDC DV, Post silicon verification and functional safety is an added advantage

Effective communication skills to interact seamlessly with all stakeholders

Must be highly focused and remain committed to obtaining closure on project goals