Nvidia Senior DFT Methodology Engineer 

United States, California 

408712960

What you'll be doing:

• As a member in our team, you will work next generation test architectures. You will work with multi-functional teams, implementing brand-new designs in test access mechanisms, high-speed test interfaces, and in-system test architecture.

• In addition, you will help develop and deploy In-System Test (IST) methodologies for our next generation products for scan architecture, ATPG, MBIST, and IOBIST applications.

• You will also help mentor junior engineers on test designs and trade-offs including cost and quality.

What we need to see:

• BSEE (or equivalent experience) with 5+, MSEE with 3+, or PhD with 2+ years of experience in DFT, system architecture, or RTL design.

• Understanding of fundamental DFT topics, such as, fault modeling, ATPG and fault simulation. Tessent ATPG/SSN experience is a plus.

• Excellent understanding of MBIST and IOBIST fundamentals.

• Experience in architecting DFT access mechanisms in 3D stacked and dielet/chiplet based designs, and UCIe protocol.

• Knowledge of high-speed interface architectures such as PCIe, USB3, DDR is a plus.

• Excellent analytical skills in verification and validation of logic on complex and multi-million gate designs using vendor tools.

• Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power.

• Experience in Silicon debug and bring-up on the ATE or SLT platforms.

• Strong programming and scripting skills in Perl, Python or Tcl desired.

• Outstanding written and oral communication skills with the curiosity to work on rare challenges.