What you’ll be doing:
Functional and IO IP development
Different IPs integration and release for custom silicon
Build SOC or sub-system, signoff function/performance and QoR
Methodology improvement for high-efficiency custom silicon development
What we need to see:
Master candidate in EE/CS or related field
Basic C/C++ knowledge is a must
Scripting knowledge (Perl/Python/Shell)
Basic digital circuit/verilog knowledge is a must
Basic verification knowledge is a must
Ways to stand out from the crowd:
Quick learner, willing to take challenges in a new field
Fluent English and good communication skills
Familiar with VCS, system Verilog and UVM
Background with ASIC design flow, like synthesis
Familiar with AMBA protocols such as AXI, ACE, CHI, ATB, etc.
משרות נוספות שיכולות לעניין אותך