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Google Senior Register-Transfer Level Design Engineer Core IP Silicon India, Karnataka, Bengaluru 397933116
Yesterday
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 10 years of work experience in RTL design.
- Experience with ASIC design methodologies for clock domain checks and reset checks.
- Experience in RTL coding using System Verilog/Verilog.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or Computer Science.
- Experience in area, power and performance design optimization.
- Experience implementing Machine Learning Accelerators, Camera ISP image processing IP, or other multimedia IPs such as Display or Video Codec.
- Experience in scripting languages, C/C++ programming and software design skills.
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