המקום בו המומחים והחברות הטובות ביותר נפגשים
What you’ll be doing:
Contribute to Validation and productization of high-speed IOs, including PCIe, NVLink and NVLink-C2C.
Ensure interoperability with connected devices and system components in complex interconnect topologies.
Deep dive into technically challenging HSIO bugs and help drive debug efforts across various teams.
Work closely and proactively with other engineering teams such as system architects, mixed signal, and design, DGX, software/firmware, HW/SW QA, operations and AE teams to drive design, development, debug and release of next generations products.
What we need to see:
BE/Btech or Mtech degree in EC/EE or equivalent experience
Minimum 2+ years working in HSIO development, bring up planning, HSIO functional and electrical validation, and/or power optimization.
Experience with chip-to-chip, die-to-die interconnects like AMBA CHI, UCIe - including understanding of process/temp/voltage sensitivity on BER would be beneficial.
Background with identifying full chip data paths for HSIO saturation and working with applications to stress test for stability.
Experience with system level and interconnect power management optimizations
Understanding of firmware/driver structures and their interaction with HW.
Strong EE fundamentals, knowledgeable in computer architecture, high speed interfaces, timing analysis, process variations, statistical error rates and power analysis.
Effective in a collaborative environment.
Ways to stand out from the crowd:
Deep understanding of technology and passionate about what you do.
Familiarity with statistical methods and tools for data analysis.
Strong collaborative and communication skills, specifically a shown ability to effectively guide and influence within a dynamic environment.
Strive to be a standout colleague and be ready to work with global teams from diverse cultural backgrounds in a high energy environment.
משרות נוספות שיכולות לעניין אותך