In this position, you will work in a diverse, dynamic, and highly energized team responsible for designing and delivering cutting-edge IP & SoC, including Intel server, PC, and automotive chips.
You will be responsible for cultivating and reinforcing Intel and group values, ensuring an inclusive work environment, managing performance, and delivering results through the team.
o Design/verification for Clock/JTAG/Analog/DFT IP
o Scan Insertion, ATPG and pattern verification
o Memory BIST insertion, validation and pattern generation
o IEEE1149.1 Boundary Scan design, iJTAG based TAP network structure, ICL, PDL etc.
o Analysis of Functional Design for Testability, including product functionality and access through external connections, BIST and Board Level Diagnostics, control of significant circuits, and isolation of functional blocks for testing
o Create and maintain DFT timing constraints, cooperate with physical design engineer for test timing signoff
o DFT specification documentation and DFT RTL coding
o Functional Pattern generation and validation
o Pattern debug on ATE with ATE engineer
o Design Verification for DFT
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant schoolwork, internships, jobs and/or research experience.o Minimum skills and Experience:o Bachelor or Master's degree in Microelectronics, Electrical/Computer Engineering or Computer Scienceo Experience in languages Verilog, System Verilog, Python, Perl, C, C++, etc.o Good knowledge in DFT methodologies such as scan test, boundary-scan design, MBIST and memory repair.o Familiar with pre-Si verification using SystemVerilog/UVM methodology gate level simulationo EDA tools such as ATPG tools, Mentor Tessent shell, SNPS SMS, VCS simulation and/or debug tools.o Silicon enabling debug or test pattern development experienceo Preferred Skills and Experienceo At least one of the key DFT aspects such as TAP/JTAG, scan/ATPG test, boundary-scan design, MBIST and memory repair.o Familiar with the DFT integration of IPo Experienced in automotive chip DFT design is the adder. Understand the automotive FUSA expectation to DFT. Familiar with the EDA tool with ISO26262 requirements. Experience in automotive DFT specific design such as LBIST/in-line self-test, ATPG for very low DPPB.We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits
