המקום בו המומחים והחברות הטובות ביותר נפגשים
Google Staff Coherent Memory System Architect Silicon Taiwan, New Taipei 386390489
10.04.2025
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
- 7 years of experience in microarchitecture and design of ASIC blocks.
- Experience in micro-architecture performance analysis, tools, and simulators.
- Experience in designing or implementing RTL for one or more blocks: CPUSs, GPUs, caches, MMUs or coherent fabrics.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or a related field.
- Experience in building build time configurable designs.
- Knowledge of HDL languages such as System Verilog, Verilog.
- Knowledge in one or more of these areas, Coherent interconnects, Caches, memory systems.
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