Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL).
Experience in micro-architecture and design of Internet Protocols (IPs) and Subsystems.
Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
Preferred qualifications:
Experience in Networking domain like Packet processing, bandwidth management, congestion control, etc.
Experience with scripting languages (e.g., Python or Perl).
Knowledge of bus architectures, fabrics, processor design, or memory hierarchies.
Knowledge of high performance and low power design techniques.