המקום בו המומחים והחברות הטובות ביותר נפגשים
Google UX Researcher Survey Scientist Search Taiwan, Taiwan Province 375927297
Yesterday
Minimum qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF).
Preferred qualifications:
- PhD in Electrical Engineering or Computer Science.
- Experience leading front-end design for modern processor components or AI accelerators.
- Experience with ARM Instruction Set Architecture.
- Experience with System on a chip design, architect, and integration.
משרות נוספות שיכולות לעניין אותך
