Job Overview:You will ensure all these products work effectively with each other and the software to enable our partners to produce outstanding systems!
Responsibilities:We're currently hiring for Senior and Staff level Verification Engineers. Your day-to-day responsibilities will depend on your level of experience, but could include:
- Your key responsibilities will include writing test plans, defining test methodologies, developing testbenches and tests, and debugging of test failures and issues.
- Working with project management and leads on planning tasks, setting schedules, and quality checkpoints.
- Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis and formal verification.
- Staff Engineers are also encouraged to mentor junior members
Required Skills and Experience :- Understanding of digital hardware design and Verilog/SystemVerilog HDL
- Experienced in one or more of various verification methodologies – UVM/OVM, formal, power aware verification, emulation
- Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support
- Experience with relevant coding languages: SystemVerilog, c++ and python
- Good Problem Solving and Debugging skills.
“Nice To Have” Skills and Experience :- Experience with ARM Architecture
- Knowledge of cache coherency protocol and AMBA protocols like CHI and AXI
- knowledge on scripting, automation