Qualcomm DSP Power Engineer 

India, Uttar Pradesh, Noida 

331870006

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

• Hands on experience in writing UPF based on power spec for block/SOC having complex power crossings

• Hands on experience in validating power intent using CLP

• Hands on experience on Power analysis using PTPX

• Understanding on issues related to MV cell (isolation, level shifter, retention etc) insertion during synthesis

• Good understanding on optimization of dynamic & leakage power during RTL development and physical implementation

• Good understanding on power correlation between Pre-Si and Post-Si

• Automation skill in TCL and/or Perl

• Good communication skill

• 8 to 12 Years experience

• Creating power spec for Qualcomm DSP IPs based on the design spec

• Power intent development using UPF for DSP IPs based on power spec

• Power intent validation at RTL level , Gate level (synthesis , PD ) using CLP

• Fixing power intent based on PA DV feedback for any issue related to power intent

• Debugging issues related to MV cell insertion during synthesis and modifying UPF accordingly

• Dynamic and Leakage power projection of DSP IPs during starting of the project

• Dynamic and Leakage power no. generation using PTPX and tracking the same at different stages of implementation flow

• Highlighting issues related to dynamic and leakage power mismatch compared to the target and working with Synthesis and PD teams to fix the issues

• Working with cross function teams (SOC, Sub System etc) for smooth handoff of power intent and Dynamic & leakage power no. at different stages of project execution

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.