Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience.
8 years of experience with EDA tool workflows in semiconductor environments.
Experience with scripting languages (e.g., Python, Bash, Tcl) for workflow automation and data visualization.
Experience developing and supporting ASIC physical design flows, methodologies in process nodes, ASIC physical design, physical design flows, and methodologies.
Experience with physical design processes (e.g., EDA tools, RTL to GDS workflows, developing checkers, and workflow auditing tools).
Preferred qualifications:
Experience in extraction of ASIC design parameters, QOR metrics, and analyzing trends.
Experience with closing blocks with multiple power regions with low power focus.
Expertise in one or more aspects of physical design implementation, including 2.5D and 3DIC integration and signoff, IP integration, chip finishing issues.
Proficiency in general software engineering principles (data structures, algorithms, profiling, optimization) and Object Oriented Programming languages such as C++.