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Google ASIC Design Engineer RTL Silicon India, Karnataka, Bengaluru 310780156
06.05.2025
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon.
- Experience with Verilog or SystemVerilog language.
- Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Estimation.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or equivalent practical experience.
- Experience with chip design flow and cross-domain involving DV, DFT, Physical Design, software.
- Experience in STA closure, DV test-plan review and coverage analysis of the sub-system and chip level verification.
- Knowledge in one or more of these areas: Processor Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.
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