Nvidia ASIC Verification Engineer 

China, Shanghai 

300139756

What you'll be doing:

• Reading design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers.

• Building block/IP testbench based on UVM methodology.

• Building test cases and regression flow. Triage failures in regression and help designer root cause the bug.

• Measuring various metrics (passing rate, functional coverage, etc.) and monitor its health.

• Analyzing functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score.

• Developing necessary tools to improve team's efficiency.

What we need to see:

• BS / MS in electrical / computer engineering and related.

• 3+ years (MS) or 5+ years (BS) working experience.

• Proficient in using simulator and related tools such as VCS, Verdi, Xcelium, etc..

• Structural thoughts on verification planning in extracting requirements and organizing stimulus legality.

• Deep understanding in System Verilog, especially in writing complex random constraints and coverage model.

• Deep understanding in UVM including phase running, factory overriding, message reporting, etc..

• Fully experienced building testbench from scratch as well as BFM modeling.

• Familiar with python programing.

• Good communication skills in English.