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Google ASIC RTL Design Engineer 
India, Karnataka, Bengaluru 
282951125

10.04.2025
Minimum qualifications:
  • Bachelor’s degree in Electrical/Computer Engineering.
  • Experience with RTL design using Verilog/System Verilog and microarchitecture.
  • Experience with a scripting language like Python or Perl.
  • Experience with ARM-based SoCs, interconnects and ASIC methodology.

Preferred qualifications:
  • Master’s degree in Electrical/Computer Engineering.
  • 3 years of experience with IP design for clocking, interconnects, peripherals.
  • Experience with methodologies for low power estimation, timing closure, synthesis.
  • Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).