Nvidia Senior System Development Engineer – PLL IO 

China, Shanghai 

276827032

What You'll Be Doing:

• Innovate and Design: Architect and design innovative system-level testing capabilities for complex silicon designs to improve quality, safety, and manufacturability.

• Collaborate and Lead: Collaborate across System Architecture, DFT, ASIC, SW/FW, platform, validation, and production teams throughout the product life cycle; Lead system-level architecture, design, productization, debugging, and deployment.

• Push the Boundary: Define roadmaps by tracking industry/market trends, collecting current product feedback, prototyping new ideas, and conducting data-driven tradeoff analysis.

• Hands-on Actions: Support silicon bring-up, validation, and debug; Coordinate product level feature deployment to achieve high product quality at aggressive schedule.

What We Need To See:

• BS or MS degree in Electrical/Computer Engineering or equivalent experience.

• 5+ years of experience in silicon system architecture, digital design, validation, and debugging in high-speed IO, ADC, DAC, PLL, Clocking and SerDes related areas.

• Depth in one or more areas of high-performance circuit (PLLs and clocking, SerDes and high-speed signaling, photonics, SRAMs, power delivery/regulation, security circuits, and high-speed logic).

• Strong EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting.

• Deep understanding of firmware/driver structures and their interaction with HW.

• Working knowledge of PVT dependencies and binning methodologies.

• Experience with Python, C/C++, tool and script development, Windows and Linux OS is a plus.

• Hands on with Lab test and measurement equipment is a plus.

• Excellent verbal communication and written, presentation skills.

• Effective in a collaborative environment.