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Google ASIC RTL Integration Manager Silicon India, Karnataka, Bengaluru 271236287
11.08.2025
Minimum qualifications:
Preferred qualifications:
- Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
- 15 years of experience in ASIC RTL design integration.
- Experience in Verilog or Systemverilog coding.
- Experience in High performance design, Multi power domains with clocking of multiple SoCs with silicon.
Preferred qualifications:
- Master’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
- Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation.
- Experience with chip design flow and understanding of cross domain involving DV DFT/Physical Design/software.
- Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.
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